Как Python и Jinja могут облегчить жизнь FPGA разработчику

module simple_mux_4habr #(
  parameter D_WIDTH = 8
) (
  input  [D_WIDTH-1:0]       data_0_i,
  input  [D_WIDTH-1:0]       data_1_i,
  input  [D_WIDTH-1:0]       data_2_i,
  input  [D_WIDTH-1:0]       data_3_i,

  input  [1:0] sel_i,

  output [D_WIDTH-1:0]       data_o
);

always @(*)
  begin
    case( sel_i )

    2'd0: 
      begin
        data_o = data_0_i;
      end

    2'd1: 
      begin
        data_o = data_1_i;
      end

    2'd2: 
      begin
        data_o = data_2_i;
      end

    2'd3: 
      begin
        data_o = data_3_i;
      end

    endcase
  end
endmodule

csr_map_template = Template(u"""
{%- macro reg_name( r ) -%}
reg_{{r.num}}_{{r.name_lowcase}}
{%- endmacro %}

{%- macro reg_name_bits( r, b ) -%}
reg_{{r.num}}_{{r.name_lowcase}}___{{b.name_lowcase}}
{%- endmacro %}

{%- macro bit_init_value( b ) -%}
{{b.width}}'h{{b.init_value}}
{%- endmacro %}

{%- macro signal( width ) -%}
[{{width-1}}:0]
{%- endmacro %}

{%- macro print_port_signal( dir, width, name, eol="," ) -%}
{{ "  %-12s %-10s %-10s" | format( dir,  signal( width ),  name+eol ) }}
{%- endmacro %}

{%- macro get_port_name( b ) -%}
{%- if b.port_signal_input -%}
{{b.name_lowcase}}_i
{%- else -%}
{{b.name_lowcase}}_o
{%- endif -%}
{%- endmacro -%}

// Generated using CSR map generator 
// https://github.com/johan92/csr-map-generator

module {{module_name}}(

{%- for p in data %}
  // Register {{p.name}} signals

{%- for b in p.bits %}
  {%- if b.port_signal_input %}
{{print_port_signal( "input", b.width, get_port_name( b ) )}}
  {%- elif b.port_signal_output %}
{{print_port_signal( "output", b.width, get_port_name( b ) )}}
  {%- endif %}
{%- endfor %}
{% endfor %}

  // CSR interface
{{print_port_signal( "input",  1,       "reg_clk_i"          ) }}
{{print_port_signal( "input",  1,       "reg_rst_i"          ) }}
{{print_port_signal( "input",  reg_d_w, "reg_wr_data_i"      ) }}
{{print_port_signal( "input",  1,       "reg_wr_en_i"        ) }}
{{print_port_signal( "input",  1,       "reg_rd_en_i"        ) }}
{{print_port_signal( "input",  reg_a_w, "reg_addr_i"         ) }}
{{print_port_signal( "output", reg_d_w, "reg_rd_data_o", ""  ) }}
);


{%- for p in data %}

// ******************************************
//        Register {{p.name}} 
// ******************************************

logic [{{reg_d_w-1}}:0] {{reg_name( p )}}_read;

{%- for b in p.bits %}
{%- if b.mode != "RO" %}
logic [{{b.width-1}}:0] {{reg_name_bits( p, b )}} = {{bit_init_value( b )}};
{%- endif %}      
{%- endfor %}

{% for b in p.bits %}
{%- if b.port_signal_output %}
always_ff @( posedge reg_clk_i or posedge reg_rst_i )
  if( reg_rst_i )
    {{reg_name_bits( p, b )}} <= {{bit_init_value( b )}};
  else 
    if( reg_wr_en_i && ( reg_addr_i == {{reg_a_w}}'h{{p.num}} ) )
      {{reg_name_bits( p, b )}} <= reg_wr_data_i[{{b.bit_msb}}:{{b.bit_lsb}}];
  {%-if b.mode == "RW_SC" %}
    else
      {{reg_name_bits( p, b )}} <= {{bit_init_value( b )}};
  {% endif %}
{%- endif %}

{%- if b.mode == "RO_LH" or b.mode == "RO_LL" %}
always_ff @( posedge reg_clk_i or posedge reg_rst_i )
  if( reg_rst_i )
    {{reg_name_bits( p, b )}} <= {{bit_init_value( b )}};
  else
    begin
      if( reg_rd_en_i && ( reg_addr_i == {{reg_a_w}}'h{{p.num}} ) )
        {{reg_name_bits( p, b )}} <= {{bit_init_value( b )}};

      {% if b.mode == "RO_LL" %}
      if( {{get_port_name( b )}} == 1'b0 )
        {{reg_name_bits( p, b )}} <= 1'b0;
      {%- elif b.mode == "RO_LH" %}
      if( {{get_port_name( b )}} == 1'b1 )
        {{reg_name_bits( p, b )}} <= 1'b1;
      {%- endif %}
    end

{% endif %}
{% endfor %}

// assigning to output
{%- for b in p.bits %}
{%- if b.port_signal_output %}
assign {{get_port_name( b )}} = {{reg_name_bits( p, b )}};
{%- endif %}
{%- endfor %}

{%- macro print_in_always_comb( r, b, _right_value ) -%}
{%- if b == "" -%}
{{ "  %s%-7s = %s;" | format( reg_name( r ) + "_read",  "",  _right_value ) }}
{%- else -%}
{{ "  %s%-7s = %s;" | format( reg_name( r ) + "_read", "["+b.bit_msb|string+":"+b.bit_lsb|string+"]" ,  _right_value ) }}
{%- endif -%}
{%- endmacro %}

// assigning to read data
always_comb
  begin
  {{print_in_always_comb( p, "", reg_d_w|string+"'h0" ) }}

{%- for b in p.bits %}
  {%- if b.mode == "RO" %}
  {{print_in_always_comb( p, b, get_port_name( b ) )}}
  {%- else %}
  {{print_in_always_comb( p, b, reg_name_bits( p, b ) )}}
  {%- endif %}
{%- endfor %}
  end

{%- endfor %}


// ******************************************
//      Reading stuff 
// ******************************************
logic [{{reg_d_w-1}}:0] reg_rd_data = {{reg_d_w}}'h0;

always_ff @( posedge reg_clk_i or posedge reg_rst_i )
  if( reg_rst_i )
    reg_rd_data <= {{reg_d_w}}'h0;
  else
    if( reg_rd_en_i )
      begin

        case( reg_addr_i )
        {% for p in data %}
        {{reg_a_w}}'h{{p.num}}:
          begin
            reg_rd_data <= {{reg_name( p )}}_read;
          end
        {% endfor %}
        default:
          begin
            reg_rd_data <= {{reg_d_w}}'h0;
          end

        endcase

      end

assign reg_rd_data_o = reg_rd_data;

endmodule
""")

// Generated using CSR map generator 
// https://github.com/johan92/csr-map-generator

module trafgen_map_4habr(
  // Register MAIN signals
  output       [0:0]      gen_en_o, 
  input        [0:0]      gen_error_i,
  output       [0:0]      gen_reset_o,

  // Register IP_DST signals
  output       [31:0]     ip_dst_o, 

  // Register FRM_SIZE signals
  output       [15:0]     frm_size_o,

  // Register FRM_CNT signals
  input        [31:0]     frm_cnt_i,


  // CSR interface
  input        [0:0]      reg_clk_i,
  input        [0:0]      reg_rst_i,
  input        [31:0]     reg_wr_data_i,
  input        [0:0]      reg_wr_en_i,
  input        [0:0]      reg_rd_en_i,
  input        [7:0]      reg_addr_i,
  output       [31:0]     reg_rd_data_o
);

// ******************************************
//        Register MAIN 
// ******************************************

logic [31:0] reg_0_main_read;
logic [7:0] reg_0_main___ip_core_version = 8'h7;
logic [0:0] reg_0_main___gen_en = 1'h0;
logic [0:0] reg_0_main___gen_error = 1'h0;
logic [0:0] reg_0_main___gen_reset = 1'h0;



always_ff @( posedge reg_clk_i or posedge reg_rst_i )
  if( reg_rst_i )
    reg_0_main___gen_en <= 1'h0;
  else 
    if( reg_wr_en_i && ( reg_addr_i == 8'h0 ) )
      reg_0_main___gen_en <= reg_wr_data_i[16:16];

always_ff @( posedge reg_clk_i or posedge reg_rst_i )
  if( reg_rst_i )
    reg_0_main___gen_error <= 1'h0;
  else
    begin
      if( reg_rd_en_i && ( reg_addr_i == 8'h0 ) )
        reg_0_main___gen_error <= 1'h0;

      
      if( gen_error_i == 1'b1 )
        reg_0_main___gen_error <= 1'b1;
    end



always_ff @( posedge reg_clk_i or posedge reg_rst_i )
  if( reg_rst_i )
    reg_0_main___gen_reset <= 1'h0;
  else 
    if( reg_wr_en_i && ( reg_addr_i == 8'h0 ) )
      reg_0_main___gen_reset <= reg_wr_data_i[31:31];
    else
      reg_0_main___gen_reset <= 1'h0;
  


// assigning to output
assign gen_en_o = reg_0_main___gen_en;
assign gen_reset_o = reg_0_main___gen_reset;

// assigning to read data
always_comb
  begin
    reg_0_main_read        = 32'h0;
    reg_0_main_read[7:0]   = reg_0_main___ip_core_version;
    reg_0_main_read[16:16] = reg_0_main___gen_en;
    reg_0_main_read[17:17] = reg_0_main___gen_error;
    reg_0_main_read[31:31] = reg_0_main___gen_reset;
  end

// ******************************************
//        Register IP_DST 
// ******************************************

logic [31:0] reg_1_ip_dst_read;
logic [31:0] reg_1_ip_dst___ip_dst = 32'hB2F8E921;


always_ff @( posedge reg_clk_i or posedge reg_rst_i )
  if( reg_rst_i )
    reg_1_ip_dst___ip_dst <= 32'hB2F8E921;
  else 
    if( reg_wr_en_i && ( reg_addr_i == 8'h1 ) )
      reg_1_ip_dst___ip_dst <= reg_wr_data_i[31:0];


// assigning to output
assign ip_dst_o = reg_1_ip_dst___ip_dst;

// assigning to read data
always_comb
  begin
    reg_1_ip_dst_read        = 32'h0;
    reg_1_ip_dst_read[31:0]  = reg_1_ip_dst___ip_dst;
  end

// ******************************************
//        Register FRM_SIZE 
// ******************************************

logic [31:0] reg_2_frm_size_read;
logic [15:0] reg_2_frm_size___frm_size = 16'h40;


always_ff @( posedge reg_clk_i or posedge reg_rst_i )
  if( reg_rst_i )
    reg_2_frm_size___frm_size <= 16'h40;
  else 
    if( reg_wr_en_i && ( reg_addr_i == 8'h2 ) )
      reg_2_frm_size___frm_size <= reg_wr_data_i[15:0];


// assigning to output
assign frm_size_o = reg_2_frm_size___frm_size;

// assigning to read data
always_comb
  begin
    reg_2_frm_size_read        = 32'h0;
    reg_2_frm_size_read[15:0]  = reg_2_frm_size___frm_size;
  end

// ******************************************
//        Register FRM_CNT 
// ******************************************

logic [31:0] reg_3_frm_cnt_read;




// assigning to output

// assigning to read data
always_comb
  begin
    reg_3_frm_cnt_read        = 32'h0;
    reg_3_frm_cnt_read[31:0]  = frm_cnt_i;
  end


// ******************************************
//      Reading stuff 
// ******************************************
logic [31:0] reg_rd_data = 32'h0;

always_ff @( posedge reg_clk_i or posedge reg_rst_i )
  if( reg_rst_i )
    reg_rd_data <= 32'h0;
  else
    if( reg_rd_en_i )
      begin

        case( reg_addr_i )
        
        8'h0:
          begin
            reg_rd_data <= reg_0_main_read;
          end
        
        8'h1:
          begin
            reg_rd_data <= reg_1_ip_dst_read;
          end
        
        8'h2:
          begin
            reg_rd_data <= reg_2_frm_size_read;
          end
        
        8'h3:
          begin
            reg_rd_data <= reg_3_frm_cnt_read;
          end
        
        default:
          begin
            reg_rd_data <= 32'h0;
          end

        endcase

      end

assign reg_rd_data_o = reg_rd_data;

endmodule